mirror of
https://github.com/linux-sunxi/meta-sunxi.git
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61 lines
2.5 KiB
Diff
61 lines
2.5 KiB
Diff
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Alejandro=20Gonz=C3=A1lez?=
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<alejandro.gonzalez.correo@gmail.com>
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Date: Sun, 25 Aug 2019 17:05:58 +0200
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Subject: [PATCH] mmc: sunxi: fix unusuable eMMC on some H6 boards by disabling
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DDR
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Some Allwinner H6 boards have timing problems when dealing with
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DDR-capable eMMC cards. These boards include the Pine H64 and Tanix TX6.
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These timing problems result in out of sync communication between the
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driver and the eMMC, which renders the memory unsuable for every
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operation but some basic commmands, like reading the status register.
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The cause of these timing problems is not yet well known, but they go
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away by disabling DDR mode operation in the driver. Like on some H5
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boards, it might be that the traces are not precise enough to support
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these speeds. However, Jernej Skrabec compared the BSP driver with this
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driver, and found that the BSP driver configures pinctrl to operate at
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1.8 V when entering DDR mode (although 3.3 V operation is supported), while
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the mainline kernel lacks any mechanism to switch voltages dynamically.
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Finally, other possible cause might be some timing parameter that is
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different on the H6 with respect to other SoCs.
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Therefore, as this fix works reliably, the kernel lacks the required
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dynamic pinctrl control for now and a slow eMMC is better than a not
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working eMMC, just disable DDR operation for now on H6-compatible
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devices.
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Signed-off-by: Alejandro González <alejandro.gonzalez.correo@gmail.com>
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---
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drivers/mmc/host/sunxi-mmc.c | 9 ++++++---
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1 file changed, 6 insertions(+), 3 deletions(-)
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--- a/drivers/mmc/host/sunxi-mmc.c
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+++ b/drivers/mmc/host/sunxi-mmc.c
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@@ -1421,14 +1421,17 @@ static int sunxi_mmc_probe(struct platfo
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/*
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* Some H5 devices do not have signal traces precise enough to
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- * use HS DDR mode for their eMMC chips.
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+ * use HS DDR mode for their eMMC chips. Other H6 devices operate
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+ * unreliably on HS DDR mode, too.
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*
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* We still enable HS DDR modes for all the other controller
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- * variants that support them.
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+ * variants that support them properly.
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*/
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if ((host->cfg->clk_delays || host->use_new_timings) &&
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!of_device_is_compatible(pdev->dev.of_node,
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- "allwinner,sun50i-h5-emmc"))
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+ "allwinner,sun50i-h5-emmc") &&
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+ !of_device_is_compatible(pdev->dev.of_node,
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+ "allwinner,sun50i-h6-emmc"))
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mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
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ret = mmc_of_parse(mmc);
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