mirror of
https://github.com/linux-sunxi/meta-sunxi.git
synced 2024-09-06 21:54:43 +02:00
303 lines
10 KiB
C
303 lines
10 KiB
C
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/*
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*
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* This file is part of pyA20.
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* mapping.h is python GPIO extension.
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*
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* Copyright (c) 2014 Stefan Mavrodiev @ OLIMEX LTD, <support@olimex.com>
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*
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* pyA20 is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#ifndef __MAPPING_H
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#define __MAPPING_H
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#include "gpio_lib.h"
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/**
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Structure that describe all gpio
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*/
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typedef struct _pin {
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char name[10]; // The processor pin
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int offset; // Memory offset for the pin
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int pin_number; // Number on the connector
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}pin_t;
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typedef struct _gpio {
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char connector_name[10];
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pin_t pins[41];
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}gpio_t;
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gpio_t gpio[] = {
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{"lcd",
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{
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{ "PD16", SUNXI_GPD(16), 5 },
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{ "PD17", SUNXI_GPD(17), 6 },
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{ "PD18", SUNXI_GPD(18), 7 },
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{ "PD19", SUNXI_GPD(19), 8 },
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{ "PD20", SUNXI_GPD(20), 9 },
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{ "PD21", SUNXI_GPD(21), 10 },
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{ "PD22", SUNXI_GPD(22), 11 },
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{ "PD23", SUNXI_GPD(23), 12 },
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{ "PD8", SUNXI_GPD(8), 13 },
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{ "PD9", SUNXI_GPD(9), 14 },
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{ "PD10", SUNXI_GPD(10), 15 },
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{ "PD11", SUNXI_GPD(11), 16 },
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{ "PD12", SUNXI_GPD(12), 17 },
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{ "PD13", SUNXI_GPD(13), 18 },
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{ "PD14", SUNXI_GPD(14), 19 },
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{ "PD15", SUNXI_GPD(15), 20 },
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{ "PD0", SUNXI_GPD(0), 21 },
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{ "PD1", SUNXI_GPD(1), 22 },
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{ "PD2", SUNXI_GPD(2), 23 },
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{ "PD3", SUNXI_GPD(3), 24 },
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{ "PD4", SUNXI_GPD(4), 25 },
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{ "PD5", SUNXI_GPD(5), 26 },
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{ "PD6", SUNXI_GPD(6), 27 },
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{ "PD7", SUNXI_GPD(7), 28 },
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{ "PD26", SUNXI_GPD(26), 29 },
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{ "PD27", SUNXI_GPD(27), 30 },
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{ "PD24", SUNXI_GPD(24), 31 },
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{ "PD25", SUNXI_GPD(25), 32 },
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{ "PH8", SUNXI_GPH(8), 35 },
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{ "PB2", SUNXI_GPB(2), 36 },
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{
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{ 0, 0, 0}
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},
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}
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},
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/*
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#define PIN_PG0 SUNXI_GPG(0)
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#define PIN_PG1 SUNXI_GPG(1)
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#define PIN_PG2 SUNXI_GPG(2)
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#define PIN_PG3 SUNXI_GPG(3)
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#define PIN_PG4 SUNXI_GPG(4)
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#define PIN_PG5 SUNXI_GPG(5)
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#define PIN_PG6 SUNXI_GPG(6)
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#define PIN_PG7 SUNXI_GPG(7)
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#define PIN_PG8 SUNXI_GPG(8)
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#define PIN_PG9 SUNXI_GPG(9)
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#define PIN_PG10 SUNXI_GPG(10)
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#define PIN_PG11 SUNXI_GPG(11)
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*/ {"gpio1",
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{
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{ "PG0", SUNXI_GPG(0), 5 },
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{ "PG1", SUNXI_GPG(0), 7 },
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{ "PG2", SUNXI_GPG(0), 9 },
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{ "PG3", SUNXI_GPG(0), 11 },
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{ "PG4", SUNXI_GPG(0), 13 },
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{ "PG5", SUNXI_GPG(0), 15 },
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{ "PG6", SUNXI_GPG(0), 17 },
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{ "PG7", SUNXI_GPG(0), 19 },
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{ "PG8", SUNXI_GPG(0), 21 },
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{ "PG9", SUNXI_GPG(0), 23 },
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{ "PG10", SUNXI_GPG(0), 25 },
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{ "PG11", SUNXI_GPG(0), 27 },
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{
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{ 0, 0, 0}
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},
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}
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},
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/*
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//GPIO 2
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#define PIN_PE0 SUNXI_GPE(0)
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#define PIN_PE1 SUNXI_GPE(1)
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#define PIN_PI0 SUNXI_GPI(0)
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#define PIN_PE2 SUNXI_GPE(2)
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#define PIN_PI1 SUNXI_GPI(1)
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#define PIN_PE3 SUNXI_GPE(3)
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#define PIN_PI2 SUNXI_GPI(2)
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#define PIN_PE4 SUNXI_GPE(4)
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#define PIN_PI3 SUNXI_GPI(3)
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#define PIN_PE5 SUNXI_GPE(5)
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#define PIN_PI10 SUNXI_GPI(10)
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#define PIN_PE6 SUNXI_GPE(6)
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#define PIN_PI11 SUNXI_GPI(11)
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#define PIN_PE7 SUNXI_GPE(7)
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#define PIN_PC3 SUNXI_GPC(3)
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#define PIN_PE8 SUNXI_GPE(8)
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#define PIN_PC7 SUNXI_GPC(7)
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#define PIN_PE9 SUNXI_GPE(9)
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#define PIN_PC16 SUNXI_GPC(16)
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#define PIN_PE10 SUNXI_GPE(10)
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#define PIN_PC17 SUNXI_GPC(17)
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#define PIN_PE11 SUNXI_GPE(11)
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#define PIN_PC18 SUNXI_GPC(18)
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#define PIN_PI14 SUNXI_GPI(14)
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#define PIN_PC23 SUNXI_GPC(23)
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#define PIN_PI15 SUNXI_GPI(15)
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#define PIN_PC24 SUNXI_GPC(24)
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#define PIN_PB23 SUNXI_GPB(23)
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#define PIN_PB22 SUNXI_GPB(22)
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*/
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{"gpio2",
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{
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{ "PE0", SUNXI_GPE(0), 6 },
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{ "PE1", SUNXI_GPE(1), 8 },
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{ "PI0", SUNXI_GPI(0), 9 },
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{ "PE2", SUNXI_GPE(2), 10 },
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{ "PI1", SUNXI_GPI(1), 11 },
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{ "PE3", SUNXI_GPE(3), 12 },
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{ "PI2", SUNXI_GPI(2), 13 },
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{ "PE4", SUNXI_GPE(4), 14 },
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{ "PI3", SUNXI_GPI(3), 15 },
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{ "PE5", SUNXI_GPE(5), 16 },
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{ "PI10", SUNXI_GPI(10), 17 },
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{ "PE6", SUNXI_GPE(6), 18 },
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{ "PI11", SUNXI_GPI(11), 19 },
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{ "PE7", SUNXI_GPE(7), 20 },
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{ "PC3", SUNXI_GPC(3), 21 },
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{ "PE8", SUNXI_GPE(8), 22 },
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{ "PC7", SUNXI_GPC(7), 23 },
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{ "PE9", SUNXI_GPE(9), 24 },
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{ "PC16", SUNXI_GPC(16), 25 },
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{ "PE10", SUNXI_GPE(10), 26 },
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{ "PC17", SUNXI_GPC(17), 27 },
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{ "PE11", SUNXI_GPE(11), 28 },
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{ "PC18", SUNXI_GPC(18), 29 },
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{ "PI14", SUNXI_GPI(14), 30 },
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{ "PC23", SUNXI_GPC(23), 31 },
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{ "PI15", SUNXI_GPI(15), 32 },
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{ "PC24", SUNXI_GPC(24), 33 },
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{ "PB23", SUNXI_GPB(23), 34 },
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{ "PB22", SUNXI_GPB(22), 36 },
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{
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{ 0, 0, 0}
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},
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}
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},
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/*
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//GPIO 3
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#define PIN_PH0 SUNXI_GPH(0)
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#define PIN_PB3 SUNXI_GPB(3)
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#define PIN_PH2 SUNXI_GPH(2)
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#define PIN_PB4 SUNXI_GPB(4)
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#define PIN_PH7 SUNXI_GPH(7)
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#define PIN_PB5 SUNXI_GPB(5)
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#define PIN_PH9 SUNXI_GPH(9)
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#define PIN_PB6 SUNXI_GPB(6)
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#define PIN_PH10 SUNXI_GPH(10)
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#define PIN_PB7 SUNXI_GPB(7)
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#define PIN_PH11 SUNXI_GPH(11)
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#define PIN_PB8 SUNXI_GPB(8)
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#define PIN_PH12 SUNXI_GPH(12)
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#define PIN_PB10 SUNXI_GPB(10)
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#define PIN_PH13 SUNXI_GPH(13)
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#define PIN_PB11 SUNXI_GPB(11)
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#define PIN_PH14 SUNXI_GPH(14)
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#define PIN_PB12 SUNXI_GPB(12)
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#define PIN_PH15 SUNXI_GPH(15)
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#define PIN_PB13 SUNXI_GPB(13)
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#define PIN_PH16 SUNXI_GPH(16)
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#define PIN_PB14 SUNXI_GPB(14)
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#define PIN_PH17 SUNXI_GPH(17)
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#define PIN_PB15 SUNXI_GPB(15)
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#define PIN_PH18 SUNXI_GPH(18)
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#define PIN_PB16 SUNXI_GPB(16)
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#define PIN_PH19 SUNXI_GPH(19)
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#define PIN_PB17 SUNXI_GPB(17)
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#define PIN_PH20 SUNXI_GPH(20)
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#define PIN_PH24 SUNXI_GPH(24)
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#define PIN_PH21 SUNXI_GPH(21)
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#define PIN_PH25 SUNXI_GPH(25)
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#define PIN_PH22 SUNXI_GPH(22)
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#define PIN_PH26 SUNXI_GPH(26)
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#define PIN_PH23 SUNXI_GPH(23)
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#define PIN_PH27 SUNXI_GPH(27)
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*/
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{"gpio3",
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{
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{ "PH0", SUNXI_GPH(0), 5 },
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{ "PB3", SUNXI_GPB(3), 6 },
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{ "PH2", SUNXI_GPH(2), 7 },
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{ "PB4", SUNXI_GPB(4), 8 },
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{ "PH7", SUNXI_GPH(7), 9 },
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{ "PB5", SUNXI_GPB(5), 10 },
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{ "PH9", SUNXI_GPH(9), 11 },
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{ "PB6", SUNXI_GPB(6), 12 },
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{ "PH10", SUNXI_GPH(10), 13 },
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{ "PB7", SUNXI_GPB(7), 14 },
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{ "PH11", SUNXI_GPH(11), 15 },
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{ "PB8", SUNXI_GPB(8), 16 },
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{ "PH12", SUNXI_GPH(12), 17 },
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{ "PB10", SUNXI_GPB(10), 18 },
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{ "PH13", SUNXI_GPH(13), 19 },
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{ "PB11", SUNXI_GPB(11), 20 },
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{ "PH14", SUNXI_GPH(14), 21 },
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{ "PB12", SUNXI_GPB(12), 22 },
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{ "PH15", SUNXI_GPH(15), 23 },
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{ "PB13", SUNXI_GPB(13), 24 },
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{ "PH16", SUNXI_GPH(16), 25 },
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{ "PB14", SUNXI_GPB(14), 26 },
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{ "PH17", SUNXI_GPH(17), 27 },
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{ "PB15", SUNXI_GPB(15), 28 },
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{ "PH18", SUNXI_GPH(18), 29 },
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{ "PB16", SUNXI_GPB(16), 30 },
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{ "PH19", SUNXI_GPH(19), 31 },
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{ "PB17", SUNXI_GPB(17), 32 },
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{ "PH20", SUNXI_GPH(20), 33 },
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{ "PH24", SUNXI_GPH(24), 34 },
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{ "PH21", SUNXI_GPH(21), 35 },
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{ "PH25", SUNXI_GPH(25), 36 },
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{ "PH22", SUNXI_GPH(22), 37 },
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{ "PH26", SUNXI_GPH(26), 38 },
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{ "PH23", SUNXI_GPH(23), 39 },
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{ "PH27", SUNXI_GPH(27), 40 },
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{
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{ 0, 0, 0}
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},
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}
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},
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{"uext1",
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{
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{ "PI12", SUNXI_GPI(12), 3 },
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{ "PI13", SUNXI_GPI(13), 4 },
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{ "PB20", SUNXI_GPB(20), 5 },
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{ "PB21", SUNXI_GPB(21), 6 },
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{ "PC22", SUNXI_GPC(22), 7 },
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{ "PC21", SUNXI_GPC(21), 8 },
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{ "PC20", SUNXI_GPC(20), 9 },
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{ "PC19", SUNXI_GPC(19), 10 },
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{
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{ 0, 0, 0}
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},
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}
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},
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{"uext2",
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{
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{ "PI20", SUNXI_GPI(20), 3 },
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{ "PI21", SUNXI_GPI(21), 4 },
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{ "PB18", SUNXI_GPB(18), 5 },
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{ "PB19", SUNXI_GPB(19), 6 },
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{ "PI19", SUNXI_GPI(19), 7 },
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{ "PI18", SUNXI_GPI(18), 8 },
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{ "PI17", SUNXI_GPI(17), 9 },
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{ "PI16", SUNXI_GPI(16), 10 },
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{
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{ 0, 0, 0}
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},
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}
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},
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};
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#endif
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