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Add MSA optimized encoder transform functions
We add the following MSA optimized encoder transform functions: - ITransform - FTransform - FTransformWHT Change-Id: Ia6b17556aba5aff2d7a88208905fb45293d080a8
This commit is contained in:
Parag Salasakar
committed by
Pascal Massimino
Pascal Massimino
parent
dce64bfa1b
commit
435308e029
@ -23,14 +23,18 @@
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#ifdef CLANG_BUILD
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#define ADDVI_H(a, b) __msa_addvi_h((v8i16)a, b)
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#define ADDVI_W(a, b) __msa_addvi_w((v4i32)a, b)
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#define SRAI_B(a, b) __msa_srai_b((v16i8)a, b)
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#define SRAI_H(a, b) __msa_srai_h((v8i16)a, b)
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#define SRAI_W(a, b) __msa_srai_w((v4i32)a, b)
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#define SRLI_H(a, b) __msa_srli_h((v8i16)a, b)
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#else
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#define ADDVI_H(a, b) (a + b)
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#define ADDVI_W(a, b) (a + b)
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#define SRAI_B(a, b) (a >> b)
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#define SRAI_H(a, b) (a >> b)
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#define SRAI_W(a, b) (a >> b)
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#define SRLI_H(a, b) (a << b)
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#endif
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#define LD_B(RTYPE, psrc) *((RTYPE*)(psrc))
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@ -257,6 +261,18 @@
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} while (0)
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#define ST_UB8(...) ST_B8(v16u8, __VA_ARGS__)
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/* Description : Store vectors of 8 halfword elements with stride
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* Arguments : Inputs - in0, in1, pdst, stride
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* Details : Store 8 halfword elements from 'in0' to (pdst)
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* Store 8 halfword elements from 'in1' to (pdst + stride)
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*/
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#define ST_H2(RTYPE, in0, in1, pdst, stride) do { \
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ST_H(RTYPE, in0, pdst); \
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ST_H(RTYPE, in1, pdst + stride); \
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} while (0)
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#define ST_UH2(...) ST_H2(v8u16, __VA_ARGS__)
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#define ST_SH2(...) ST_H2(v8i16, __VA_ARGS__)
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/* Description : Store 2x4 byte block to destination memory from input vector
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* Arguments : Inputs - in, stidx, pdst, stride
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* Details : Index 'stidx' halfword element from 'in' vector is copied to
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@ -377,6 +393,22 @@
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} while (0)
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#define DOTP_SB2_SH(...) DOTP_SB2(v8i16, __VA_ARGS__)
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/* Description : Dot product & addition of halfword vector elements
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* Arguments : Inputs - mult0, mult1, cnst0, cnst1
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* Outputs - out0, out1
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* Return Type - as per RTYPE
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* Details : Signed halfword elements from 'mult0' are multiplied with
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* signed halfword elements from 'cnst0' producing a result
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* twice the size of input i.e. signed word.
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* The multiplication result of adjacent odd-even elements
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* are added to the 'out0' vector
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*/
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#define DPADD_SH2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1) do { \
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out0 = (RTYPE)__msa_dpadd_s_w((v4i32)out0, (v8i16)mult0, (v8i16)cnst0); \
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out1 = (RTYPE)__msa_dpadd_s_w((v4i32)out1, (v8i16)mult1, (v8i16)cnst1); \
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} while (0)
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#define DPADD_SH2_SW(...) DPADD_SH2(v4i32, __VA_ARGS__)
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/* Description : Clips all signed halfword elements of input vector
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* between 0 & 255
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* Arguments : Input/output - val
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@ -434,6 +466,22 @@ static WEBP_INLINE uint32_t func_hadd_uh_u32(v8u16 in) {
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}
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#define HADD_UH_U32(in) func_hadd_uh_u32(in)
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/* Description : Horizontal subtraction of unsigned byte vector elements
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* Arguments : Inputs - in0, in1
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* Outputs - out0, out1
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* Return Type - as per RTYPE
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* Details : Each unsigned odd byte element from 'in0' is subtracted from
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* even unsigned byte element from 'in0' (pairwise) and the
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* halfword result is written to 'out0'
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*/
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#define HSUB_UB2(RTYPE, in0, in1, out0, out1) do { \
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out0 = (RTYPE)__msa_hsub_u_h((v16u8)in0, (v16u8)in0); \
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out1 = (RTYPE)__msa_hsub_u_h((v16u8)in1, (v16u8)in1); \
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} while (0)
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#define HSUB_UB2_UH(...) HSUB_UB2(v8u16, __VA_ARGS__)
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#define HSUB_UB2_SH(...) HSUB_UB2(v8i16, __VA_ARGS__)
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#define HSUB_UB2_SW(...) HSUB_UB2(v4i32, __VA_ARGS__)
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/* Description : Set element n input vector to GPR value
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* Arguments : Inputs - in0, in1, in2, in3
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* Output - out
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@ -745,6 +793,23 @@ static WEBP_INLINE uint32_t func_hadd_uh_u32(v8u16 in) {
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#define PCKEV_B4_SH(...) PCKEV_B4(v8i16, __VA_ARGS__)
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#define PCKEV_B4_SW(...) PCKEV_B4(v4i32, __VA_ARGS__)
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/* Description : Pack even halfword elements of vector pairs
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* Arguments : Inputs - in0, in1, in2, in3
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* Outputs - out0, out1
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* Return Type - as per RTYPE
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* Details : Even halfword elements of 'in0' are copied to the left half of
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* 'out0' & even halfword elements of 'in1' are copied to the
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* right half of 'out0'.
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*/
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#define PCKEV_H2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
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out0 = (RTYPE)__msa_pckev_h((v8i16)in0, (v8i16)in1); \
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out1 = (RTYPE)__msa_pckev_h((v8i16)in2, (v8i16)in3); \
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} while (0)
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#define PCKEV_H2_UH(...) PCKEV_H2(v8u16, __VA_ARGS__)
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#define PCKEV_H2_SH(...) PCKEV_H2(v8i16, __VA_ARGS__)
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#define PCKEV_H2_SW(...) PCKEV_H2(v4i32, __VA_ARGS__)
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#define PCKEV_H2_UW(...) PCKEV_H2(v4u32, __VA_ARGS__)
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/* Description : Arithmetic immediate shift right all elements of word vector
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* Arguments : Inputs - in0, in1, shift
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* Outputs - in place operation
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@ -814,6 +879,30 @@ static WEBP_INLINE uint32_t func_hadd_uh_u32(v8u16 in) {
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#define ADDVI_H2_SH(...) ADDVI_H2(v8i16, __VA_ARGS__)
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#define ADDVI_H2_UH(...) ADDVI_H2(v8u16, __VA_ARGS__)
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/* Description : Addition of 2 pairs of word vectors
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* Arguments : Inputs - in0, in1, in2, in3
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* Outputs - out0, out1
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* Details : Each element in 'in0' is added to 'in1' and result is written
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* to 'out0'.
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*/
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#define ADDVI_W2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
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out0 = (RTYPE)ADDVI_W(in0, in1); \
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out1 = (RTYPE)ADDVI_W(in2, in3); \
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} while (0)
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#define ADDVI_W2_SW(...) ADDVI_W2(v4i32, __VA_ARGS__)
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/* Description : Fill 2 pairs of word vectors with GP registers
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* Arguments : Inputs - in0, in1
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* Outputs - out0, out1
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* Details : GP register in0 is replicated in each word element of out0
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* GP register in1 is replicated in each word element of out1
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*/
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#define FILL_W2(RTYPE, in0, in1, out0, out1) do { \
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out0 = (RTYPE)__msa_fill_w(in0); \
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out1 = (RTYPE)__msa_fill_w(in1); \
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} while (0)
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#define FILL_W2_SW(...) FILL_W2(v4i32, __VA_ARGS__)
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/* Description : Addition of 2 pairs of vectors
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* Arguments : Inputs - in0, in1, in2, in3
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* Outputs - out0, out1
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@ -842,6 +931,32 @@ static WEBP_INLINE uint32_t func_hadd_uh_u32(v8u16 in) {
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out1 = in2 - in3; \
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} while (0)
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/* Description : Addition - Subtraction of input vectors
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* Arguments : Inputs - in0, in1
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* Outputs - out0, out1
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* Details : Each element in 'in1' is added to 'in0' and result is
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* written to 'out0'.
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* Each element in 'in1' is subtracted from 'in0' and result is
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* written to 'out1'.
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*/
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#define ADDSUB2(in0, in1, out0, out1) do { \
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out0 = in0 + in1; \
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out1 = in0 - in1; \
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} while (0)
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/* Description : Sign extend halfword elements from right half of the vector
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* Arguments : Input - in (halfword vector)
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* Output - out (sign extended word vector)
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* Return Type - signed word
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* Details : Sign bit of halfword elements from input vector 'in' is
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* extracted and interleaved with same vector 'in0' to generate
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* 4 word elements keeping sign intact
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*/
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#define UNPCK_R_SH_SW(in, out) do { \
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const v8i16 sign_m = __msa_clti_s_h((v8i16)in, 0); \
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out = (v4i32)__msa_ilvr_h(sign_m, (v8i16)in); \
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} while (0)
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/* Description : Sign extend halfword elements from input vector and return
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* the result in pair of vectors
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* Arguments : Input - in (halfword vector)
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