From f1c7ec07e16401baeb014a830a1176118148928c Mon Sep 17 00:00:00 2001
From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
Date: Mon, 31 Aug 2015 22:17:04 +0200
Subject: [PATCH] Created PCIe interface (markdown)

---
 PCIe-interface.md | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)
 create mode 100644 PCIe-interface.md

diff --git a/PCIe-interface.md b/PCIe-interface.md
new file mode 100644
index 0000000..1d02a9e
--- /dev/null
+++ b/PCIe-interface.md
@@ -0,0 +1,26 @@
+# PCIe registers
+These registers sits on PCI Bar 0 and is related to the PCIe to S2 SoC interface (probably from Broadcom). They relate to PLL settings and power/link states.
+
+### 0:0xd000
+Possibly used to set the PCIe link state.
+* Written values: 0x10 (L1 state?)
+
+### 0:0xd120
+* Written values: 0x1804
+
+### 0:0xd124
+Possibly information on PLL power state.
+* Written values: 0xac5800
+* Compared values: 0xac5800
+
+### 0:0xd128
+* Written values: 0x1f08, 0x1608, 0x1708
+
+### 0:0xd12c
+* Written values: 0x800005bf, 0x80008610, 0x8000fc00
+
+### Logic
+* Put PCIe link into L1 state
+* Turn off PLL
+* Check if PLL actually turned off (fail if not)
+* Do initialization sequence on 0xd128 and 0x12c
\ No newline at end of file