diff --git a/S2-PLLs.md b/S2-PLLs.md
index af6a7dd..7f872e7 100644
--- a/S2-PLLs.md
+++ b/S2-PLLs.md
@@ -27,12 +27,16 @@ PLL settings for both 24MHz and 25MHz
  * 450MHz @ 25MHz: 0x19280904
 
 ### 0:0x2c
-Used during PLL reset
+Used during PLL reset sequence.
 * Written to values: 0x0, 0x40
 
 ### 0:0x9c
 Used for DDR PHY soft reset sequence.
-* Written to values: 0xfffff
+* Written to values: 0xffbff, 0xfffff
+
+### 0:0xa8
+Used for DDR PHY soft reset sequence.
+* Written to values: 0x281
 
 ### 0:0x100
 Used during PLL reset
@@ -44,4 +48,18 @@ PLL settings for 25MHz
  * 200MHz: 0x00400078
  * 300MHz: 0x00480078
  * 400MHz: 0x00400078
- * 450MHz: 0x0048007d
\ No newline at end of file
+ * 450MHz: 0x0048007d
+
+### S2 PLL soft reset logic
+* Write 0x40 to 0:0x2c
+* Write 0x0 to 0:0x2c
+* Write 0xbcbc1500 to 0:0x100
+* Write 0x0 to 0:0x14
+* Wait for 10ms
+* Write 0x3 to 0:0x14
+
+### S2 DDR PHY soft reset logic
+* Write 0x281 to 0:0xa8
+* Write 0xfffff to 0:0x9c
+* Wait for 10ms
+* Write 0xffbff to 0:0x9c
\ No newline at end of file