From e6737571fbda60cfa68cb4b8e5dd933519c7199e Mon Sep 17 00:00:00 2001 From: Patrik Jakobsson Date: Sun, 22 Mar 2015 00:05:11 +0100 Subject: [PATCH] bcwc_pcie: Name S2_DDR40_PHY_DQ_CALIB_STATUS register Signed-off-by: Patrik Jakobsson --- bcwc_ddr.c | 2 +- bcwc_reg.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/bcwc_ddr.c b/bcwc_ddr.c index bd36e03..fcaf385 100644 --- a/bcwc_ddr.c +++ b/bcwc_ddr.c @@ -444,7 +444,7 @@ static int bcwc_ddr_generic_shmoo_rd_dqs(struct bcwc_private *dev_priv) } } - reg_val = (BCWC_S2_REG_READ(S2_DDR40_2850) >> 20) & 0x3f; + reg_val = (BCWC_S2_REG_READ(S2_DDR40_PHY_DQ_CALIB_STATUS) >> 20) & 0x3f; locked = 0; retries = 1000; diff --git a/bcwc_reg.h b/bcwc_reg.h index f138f9f..57b8c3b 100644 --- a/bcwc_reg.h +++ b/bcwc_reg.h @@ -90,7 +90,7 @@ #define S2_DDR40_PHY_VDL_CTL 0x2848 #define S2_DDR40_PHY_VDL_STATUS 0x284c -#define S2_DDR40_2850 0x2850 +#define S2_DDR40_PHY_DQ_CALIB_STATUS 0x2850 #define S2_DDR40_PHY_VDL_CHAN_STATUS 0x2854 #define S2_DDR40_PHY_VTT_CTL 0x285c