diff --git a/bcwc_hw.c b/bcwc_hw.c
index 315332f..d1a2c41 100644
--- a/bcwc_hw.c
+++ b/bcwc_hw.c
@@ -14,7 +14,7 @@
 #include "bcwc_hw.h"
 
 /* Used after most PCI Link IO writes */
-inline void bcwc_hw_pci_post(struct bcwc_private *dev_priv)
+static inline void bcwc_hw_pci_post(struct bcwc_private *dev_priv)
 {
 	pci_write_config_dword(dev_priv->pdev, 0, 0x12345678);
 }
@@ -32,7 +32,7 @@ static int bcwc_hw_s2_pll_reset(struct bcwc_private *dev_priv)
 	BCWC_S2_REG_WRITE(0x0, S2_PLL_CTRL_2C);
 	bcwc_hw_pci_post(dev_priv);
 
-	BCWC_S2_REG_WRITE(0xBCBC1500, S2_PLL_CTRL_100);
+	BCWC_S2_REG_WRITE(0xbcbc1500, S2_PLL_CTRL_100);
 	bcwc_hw_pci_post(dev_priv);
 
 	BCWC_S2_REG_WRITE(0x0, S2_PLL_CTRL_14);
@@ -73,15 +73,22 @@ static int bcwc_hw_s2_init_pcie_link(struct bcwc_private *dev_priv)
 		return -EIO;
 	}
 
-	dev_info(&dev_priv->pdev->dev, "S2 PCIe link init succeded\n");
+	/* PLL is powered down */
+	dev_info(&dev_priv->pdev->dev, "S2 PCIe link init succeeded\n");
 
-	BCWC_S2_REG_WRITE(0xf108, S2_PCIE_LINK_D128);
+	BCWC_S2_REG_WRITE(0x1f08, S2_PCIE_LINK_D128);
+	bcwc_hw_pci_post(dev_priv);
+
+	BCWC_S2_REG_WRITE(0x80008610, S2_PCIE_LINK_D12C);
+	bcwc_hw_pci_post(dev_priv);
+
+	BCWC_S2_REG_WRITE(0x1608, S2_PCIE_LINK_D128);
 	bcwc_hw_pci_post(dev_priv);
 
 	BCWC_S2_REG_WRITE(0x8000fc00, S2_PCIE_LINK_D12C);
 	bcwc_hw_pci_post(dev_priv);
 
-	BCWC_S2_REG_WRITE(0xf108, S2_PCIE_LINK_D128);
+	BCWC_S2_REG_WRITE(0x1f08, S2_PCIE_LINK_D128);
 	bcwc_hw_pci_post(dev_priv);
 
 	BCWC_S2_REG_WRITE(0x80008610, S2_PCIE_LINK_D12C);
@@ -177,14 +184,15 @@ static int bcwc_hw_s2_pll_init(struct bcwc_private *dev_priv, u32 ddr_speed)
 		reg = BCWC_S2_REG_READ(S2_PLL_STATUS_0C);
 		udelay(10);
 		retries++;
-	} while ((reg & 0x80) == 0 && retries <= 10000);
+	} while ((reg & 0x8000) == 0 && retries <= 10000);
 
 	if (retries > 10000) {
 		dev_info(&dev_priv->pdev->dev, "Failed to lock PLL: 0x%x\n",
 			 reg);
 		return -EINVAL;
 	} else {
-		dev_info(&dev_priv->pdev->dev, "PLL is locked\n");
+		dev_info(&dev_priv->pdev->dev, "PLL is locked after %d us\n",
+			 (retries * 10));
 	}
 
 	reg = BCWC_S2_REG_READ(S2_PLL_STATUS_A8);
@@ -211,7 +219,7 @@ static int bcwc_hw_s2_preinit_ddr_controller_soc(struct bcwc_private *dev_priv)
 	bcwc_hw_pci_post(dev_priv);
 	BCWC_S2_REG_WRITE(0x203, S2_DDR_REG_1108);
 	bcwc_hw_pci_post(dev_priv);
-	BCWC_S2_REG_WRITE(0x203, S2_DDR_REG_110c);
+	BCWC_S2_REG_WRITE(0x203, S2_DDR_REG_110C);
 	bcwc_hw_pci_post(dev_priv);
 	BCWC_S2_REG_WRITE(0x203, S2_DDR_REG_1110);
 	bcwc_hw_pci_post(dev_priv);
diff --git a/bcwc_reg.h b/bcwc_reg.h
index 26d25ed..bf2e795 100644
--- a/bcwc_reg.h
+++ b/bcwc_reg.h
@@ -25,7 +25,7 @@
 #define S2_DDR_REG_1100		0x1100
 #define S2_DDR_REG_1104		0x1104
 #define S2_DDR_REG_1108		0x1108
-#define S2_DDR_REG_110c		0x110c
+#define S2_DDR_REG_110C		0x110c
 #define S2_DDR_REG_1110		0x1110
 #define S2_DDR_REG_1114		0x1114
 #define S2_DDR_REG_1118		0x1118
@@ -34,12 +34,11 @@
 #define DDR_PHY_REG_BASE	0x2800
 #define DDR_PHY_NUM_REGS	127 /* Found in AppleCamIn::Start() */
 
-/* On iomem with pointer at ...fill me in... */
 #define S2_PLL_STATUS_04	0x04
 #define S2_PLL_REFCLK		(1 << 3) /* 1 = 25MHz, 0 = 24MHz */
 
 #define S2_PLL_STATUS_0C	0x0c	/* Register is called CMU_R_PLL_STS_MEMADDR */
-#define S2_PLL_STATUS_LOCKED	(1 << 7) /* 1 = PLL locked, 0 = PLL not locked */
+#define S2_PLL_STATUS_LOCKED	(1 << 15) /* 1 = PLL locked, 0 = PLL not locked */
 
 #define S2_PLL_STATUS_A8	0xa8
 #define S2_PLL_BYPASS		(1 << 0) /* 1 = bypass, 0 = non-bypass */