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bcwc_pcie: Add function for DDR PHY soft reset

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Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
This commit is contained in:
Patrik Jakobsson
2014-05-05 23:16:40 +02:00
parent d6ee0d214b
commit 26f9bb6259
1 changed files with 18 additions and 1 deletions
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19
bcwc_hw.c
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@@ -233,6 +233,23 @@ static int bcwc_hw_s2_preinit_ddr_controller_soc(struct bcwc_private *dev_priv)
return 0; return 0;
} }
static int bcwc_hw_ddr_phy_soft_reset(struct bcwc_private *dev_priv)
{
/* Clear status bits? */
BCWC_S2_REG_WRITE(0x281, S2_PLL_STATUS_A8);
bcwc_hw_pci_post(dev_priv);
BCWC_S2_REG_WRITE(0xfffff, S2_PLL_CTRL_9C);
bcwc_hw_pci_post(dev_priv);
udelay(10000);
BCWC_S2_REG_WRITE(0xffbff, S2_PLL_CTRL_9C);
bcwc_hw_pci_post(dev_priv);
return 0;
}
static int bcwc_hw_s2_init_ddr_controller_soc(struct bcwc_private *dev_priv) static int bcwc_hw_s2_init_ddr_controller_soc(struct bcwc_private *dev_priv)
{ {
u32 cmd; u32 cmd;
@@ -264,7 +281,7 @@ static int bcwc_hw_s2_init_ddr_controller_soc(struct bcwc_private *dev_priv)
/* Default to 450 MHz DDR speed for now */ /* Default to 450 MHz DDR speed for now */
bcwc_hw_s2_pll_init(dev_priv, 450); bcwc_hw_s2_pll_init(dev_priv, 450);
/* DDR PHY soft reset */ bcwc_hw_ddr_phy_soft_reset(dev_priv);
/* FIXME: Unfinished */ /* FIXME: Unfinished */